Kennedy Caisley

I am a second-year PhD student working on mixed-signal integrated circuit design at the Research and Technology Center for Detector Physics (FTD), University of Bonn, Germany.

My current research is focused on radiation-hard timing circuits - namely time-to-digital converters and clock generators. I am striving to conduct this work using automated design scripts to improve design speed, reuse, modification, and documentation.

Contact: Email | Github

Works

[1]
A. Krieger, K. Caisley, M. Garcia-Sciveres, C. Grace, and T. Heim, “Characterization of the BigRock 28 nm fast timing analog front end,” TWEPP. 2023. Forthcoming.
[2]
M. Mansour et al., “A fast, low jitter, and low time-walk multi-channel front-end IC for diamond and silicon radiation detectors,” IEEE Transactions on Nuclear Science, vol. 70, no. 7, pp. 1514–1524, 2023, doi: 10.1109/TNS.2023.3283220
[3]
K. Caisley, “A monolithic radiation-hard testbed for timing characterization of charge-sensitive particle detector front-ends in 28 nm CMOS.” Ohio State University, 2022. Available: OhioLink
[4]
K. Caisley, M. Garcia-Sciveres, and A. Krieger, “Timing performance of 28 nm hybrid pixel analog front end,” LBNL SULI Poster Session (Remote). 2021. Available: Fourwaves